Multiport Double Data Rate SDRAM controller
The DDR_PORT_CTRL IP core is a core used for interfacing between DDR DRAM memory and multiple bidirectional asynchronous user data ports with a simple interface protocol. Since the IP will normally run at a higher rate than the user ports, the high bandwidth of the DDR may be utilized.
Product key features:
The DDR SDRAM controller provides all the required sequencing of control signals, address lines and provides/captures data and converts it from/to double data rate format to/from single data rate, double width (32 bits) format. The controller is designed to interface to a single 16-bit wide memory chip, running at around 130 MHz. The IP also provides the initiation of refresh cycles every 15 µs, using the on-chip autorefresh feature. Using generic seettings, the column and row width may be selected, as well as the number of user ports implemented. The user port provides a means to read from and write data to the memory at another clock speed, lower than and up to IP's clock speed, using a 8 word buffer and a simple set of handshaking signals. The IP will arbitrate fairly between the user ports and will initiate read and write sequences as requested by the user port. Single read/write, 4-word burst reads and 8-word burst read/writes may be requested and multiple requests from user ports will be pipelined in an optimal way. Up to four memory bank ”rows” may be activated and opened at a time, resulting in a highly reduced access time whenever one of the same rows are accessed again in a successive user request. This enables even higher throughput when accesses are sequencial, which is the case for most functions (video refresh, DMA transfers, linear program execution etc). Typical maximum bandwidth is 350 Mbytes/s bandwidth which is to be compared to a theoretical limit of 512 Mbytes/s. The longer the bursts and the more sequential the access, the higher the bandwidth.
The IP core is accompanied by the OPB_DDR_IF IP core, which enables the connection of a user port to a 32-bit wide OPB bus (documented separately).
- Small footprint.
- Up to 350 MB/s bandwidth from a single DRAM chip
- Up to 128 MB of capcity (using 1gigabit chip)
- Up to four memory ports avoids bus bottleneck and allows for better bandwidth utilisation
- OPB bus to DRAM port interface available
- Fast Cache Link to DRAM port interface available
- Separated DRAM and user clock domains, allows for faster memory speeds
- Intelligent page address caching, avoiding unneccesary precharge commands